Prior art power ICs such as, for example, JP-A-2001-196587 (hereafter referred to as “Patent Publication 1”) disclose that an ONO film capable of improving a gate lifetime may be used as a gate insulating film in a power IC. FIG. 6 shows a sectional structure of such a power IC.
In a trench gate type IGBT or a MOS transistor, as shown in FIG. 6, there is used an ONO film J4 which is made of a three-layered structure film composed of a silicon oxide film J1, a silicon nitride film J2, and a silicon oxide film J3. If this ONO film J4 is used, the electrolytic concentration at the corner portions in a trench gate type semiconductor device, for example, can be prevented by the electrolytic relaxing effect of the silicon nitride film J2, thereby to improve the gate withstand voltage.
The electrolytic relaxing effect in the trench corner portions can be obtained by forming thick silicon oxide films J5 and J6 in the upper portion and in the bottom portion of the trench by using that ONO film J4 at the trench side wall portions in the trench gate type semiconductor device.
This ONO film J4 is formed in the following manner. First, the silicon oxide film J1 to become the first oxidized film is formed on the substrate surface to have a thickness of about 40 nm by a thermal oxidization. Subsequently, the silicon nitride film J2 is formed on the surface of that silicon oxide film J1 to have a thickness of about 15 nm by a CVD method. After this, the silicon oxide film J3 to become a second oxidized film on the surface of the silicon nitride film J2 by a thermal oxidization. Thus, the ONO film J4 is formed.
On a trench gate type power device using the aforementioned ONO film J4, high-temperature gate bias tests were executed by applying at a temperature of 150° C., for example, a voltage of +20 V to a gate electrode J7. These tests have revealed such a problem that the threshold value fluctuated to the minus side with the time lapse.
FIG. 7 is an energy band diagram of the case, in which the ONO film J4 is used as the gate insulating film of the trench gate type power device, and presents the energy band diagram at an n+-type source area J8 made of Si, as shown in FIG. 6, at the ONO film J4 made of the three-layered structure film of the silicon oxide film J1, the silicon nitride film J2, the silicon oxide film J3, and at the gate electrode J7 made of Poly Si.
As a phenomenon intrinsic to the ONO film, there is the charge trap phenomenon, in which carriers are stored in the ONO film by a gate bias used for the memory effect of an EPROM thereby to fluctuate a threshold voltage (as will be called the “Vth”). In case the ONO film J4 having the aforementioned structure is used, holes are trapped in the silicon nitride film J2 from the + terminal side of a + side electrode through the silicon oxide film J3 by exemplifying the + side electrode by the gate electrode J7 adjoining the second oxidized film, as shown in FIG. 7. It is, therefore, thought that the plus voltage is apparently applied to cause the aforementioned problems.
The power IC adopts the structure, in which a plurality of cells are connected in parallel to retain an electric current. If, therefore, the Vth of partial cells is lowered by the Vth fluctuation, the electric current is concentrated at the Vth-lowered cells. As a result, the element may be broken.